1. Field of the Invention
The present invention relates to a power semiconductor device.
2. Related Background Art
An ON resistance of a power semiconductor device, particularly, a vertical-type power MOSFET largely depends on electric resistance of a conductive layer (a drift layer) portion. On the other hand, a doping concentration determining the electric resistance of the drift layer can not be raised so as to exceed a limiting value determined according to a breakdown voltage of a p-n junction which a base layer and the drift layer forms. That is, a relationship of a tradeoff is present between a device breakdown voltage and the ON resistance.
In order to realize a power semiconductor device for low power dissipation, it is necessary to reduce an ON resistance while securing device breakdown voltage, namely to improve the relationship of a tradeoff.
As far as the same structure is employed in the power semiconductor device, limitation in improvement depending on device material is present in the relationship of a tradeoff between the device breakdown voltage and the ON resistance. Therefore, in order to exceed the limitation to realize a device having an ON resistance lower than that of an existing power semiconductor device, improvement in structure itself of a power semiconductor device will constitute powerful solving means.
As one example of a structure of a power MOSFET developed to realize a high breakdown voltage and a low ON resistance, one where a super-junction structure with p type pillar layers and n type pillar layers, each pillar layer having a column-like sectional structure, formed alternately is embedded in a drift layer has been known.
In the super-junction structure, a low ON resistance exceeding the limitation in material dependency can be realized by adjusting impurity amounts contained in each p type layer and each n type layer, namely, adjusting impurity concentrations of the p type pillar layer and the n type pillar layer to almost equal values, to form a non-doped layer in a dummy manner and ensure a high breakdown voltage while causing current to flow through the n typed pillar layer heavily doped. Incidentally, in order to ensure a high device breakdown voltage, it is necessary to control the impurity amounts included in the p type pillar layer and the n type pillar layer with a high precision.
Termination structures of a power MOSFET having a drift layer formed with the super-junction structure as described above are roughly classified to two kinds. The first structure lies in that a super-junction structure is formed even in a device termination section. For example, please see Japanese Patent Application Laid-Open No. 2003-115589 Publication. The second structure lies in that a super-junction structure is not formed in a device termination section. For example, see Japanese Patent Application Laid-Open No. 2000-277726 Publication.
A power MOSFET having a device termination section formed with a super-junction structure has such an advantage that, since p type pillar layers and n type pillar layers may be formed with the same mask width over an entire device including even a device section (a cell section) and device termination sections, fluctuation on a process is reduced and it is relatively easy to manufacture such a power MOSFET. However, there is such a problem that, when impurity amounts in each p type pillar layer and each n type pillar layer becomes uneven, a breakdown voltage at the device termination section is reduced largely as compared with a breakdown voltage at the cell section.
On the other hand, in a power MOSFET where a super-junction structure is not formed at a device termination section, lowering of a breakdown voltage at the device termination section when impurity amounts in each p type pillar layer and each n type pillar layer become uneven is relatively small. However, in order to balance an inside of the cell section and an outermost portion of the cell section nearest to the device termination section at a time of depletion layer forming, an impurity concentration of an outermost portion in a super-junction structure, namely, of a p type pillar layer or a n type pillar layer positioned nearest to the device termination section must be adjusted to be lower than that of the other p type pillar layers and n type pillar layers of the cell section, ideally, to be about half thereof.
In the super-junction structure, a depletion layer extends from a junction between the p type pillar layer and the n type pillar layer so that a drift layer is completely depleted at a low voltage. Since n type pillar layers are formed both sides of a p type pillar layer inside the cell section, depletion layers extend from both the sides of the p type pillar layer to join together, thereby forming a depletion layer obtained by complete depletion.
On the other hand, in the outermost pillar layer of the cell section nearest to the device termination section, since an opposite conductive type pillar layer is formed on one side but a high resistance layer is formed on the other side, a depletion layer extends only from one direction.
Accordingly, for forming depletion layers in the inside of the cell section and the outermost portion therein at a time of complete depleting approximately simultaneously, adjustment must be made so as to make a substantial thickness, in a horizontal direction, of the outermost pillar layer thinner than that of each pillar layer inside the cell section, ideally reduce the former to about half of the latter or make an impurity concentration of the outermost pillar layer lower than that of each of the remaining pillar layers, ideally reduce the former to about half of the latter.
However, in order to adjust the impurity concentration in the pillar layer, there is a difficulty on manufacturing, as described below. As a manufacturing method of a power MOSFET where a super-junction structure is not formed in a device termination section, a case of performing ion implantation and embedding crystalline growth, which is a representative process, will be considered. In this case, after ion implantation is performed for a p type pillar layer and n type pillar layer formation, a high resistance layer is formed in an embedding manner by conducting crystalline growth. After these steps are repeated plural times, connection for the pillar layers is performed by diffusion. An impurity amount in the pillar layer is controlled by adjustment of a dose amount of ion implantation and a width of a resist mask.
In order to change the impurity concentration in each p type pillar layer or each n type pillar layer according to its position, it is necessary to change the dose amount of ion implantation according to the position or change an opening width of a mask for ion implantation according to the position.
Now, in a method for changing the dose amount of ion implantation according to the position, the ion implantation and embedding crystalline growth are repeated plural times, as described above, but the ion implantation step for each time must be performed in two-stage manner, which results in lowering in throughput.
On the other hand, when the opening width of the mask for ion implantation is changed according to the position, since ion implantation is simultaneously performed for the inside of the cell section and the outermost pillar layer formation, dose amounts in the respective portions become equal. Accordingly, it becomes necessary to change the opening width of the mask for ion implantation according to the position. That is, an opening width of a mask for the outermost pillar layer formation in the cell section must be smaller than the opening width of the mask for pillar layer formation for the inside of the cell section, for example, the former must be reduced to about half of the latter.
Changing an opening width of a resist mask formed by photolithography according to the position can be easily realized technically.
However, when the resist mask is formed by the photolithography, a difference in size conversion between a reticle and an actual implantation resist mask occurs, so that the opening width of the actual resist mask is eventually different from the size on the reticle.
Fluctuation in size conversion difference in photolithography easily occurs, which causes the same result as fluctuation in impurity amount.
Accordingly, in the power MOSFET where a super-junction structure is not formed in a device termination section, when impurity amounts contained in the p type pillar layer and the n type pillar layer become uneven, lowering of a breakdown voltage in the device termination section is relatively small, but the impurity amounts in the p type pillar layer and the n type pillar layer easily fluctuates on a manufacturing process. As a result, there is such a problem that individuals with a low device breakdown voltage occur easily.